Direct chip attach (DCA) or high temperature flip-chip bonding is currently used in the semiconductor industry to physically and electrically connect a semiconductor chip to the next level of interconnection wiring. For example, the next level interconnect may be a ceramic chip carrier or an organic printed circuit (PC) board. One method of DCA involves depositing solder bumps on wettable bonding pads on a semiconductor die. These solder bumps are then soldered to traces on the next level interconnect to link the die's internal functional portions to the next level interconnect.
The bonding pads provide both the physical bond to the die surface and the electrical link into the actual circuitry of the semiconductor die. Additionally, the bonding pads provide an adhesive connection to the subsequently deposited solder bumps. The wettable bonding pads are usually prepared by selectively depositing a series of localized pad limiting metallurgy (PLM) or under bump metallurgy (UBM) by evaporation through a mask onto a semiconductor wafer. Alternatively, a blanket film of these materials can be deposited directly onto the wafer and then selectively etched to leave the wettable bonding pads in the selected areas. The metallurgy is typically composed of a chrome-copper-gold stack, although titanium or titanium/tungsten have been used as alternatives to chrome, and nickel has been used as an alternative to copper. The gold layer at the top of the stack prevents oxidation of the copper in these PLMs. The total thickness of the layers is typically approximately 5,000 to 20,000 Angstroms.
After the PLM has been deposited, the solder bumps are formed in two steps using the same or a similar mask as that used to form the wettable bonding pads. Typically, this bump material is composed of lead and tin which are deposited as a two-layer stack. In the first step lead and tin are deposited in the following order. A layer of lead, approximately 100-125 microns, is deposited first followed by a separate layer of tin, approximately 2.5 to 18 microns. As deposited, the shape of the solder bumps resembles a truncated column with a thick lead base and a thin tin cap.
The second step of the solder bump formation involves a high temperature reflow of the as-deposited bumps at temperatures in excess of 355.degree. C. to complete the compositional blending of the lead and tin layers. The near-spherical bump produced by this method typically contains about 2-10% tin, depending on the starting deposited thickness ratios. During the reflow process, the tin layer at the top of a as-deposited solder bump diffuses through the lead layer to form a copper/tin intermetallic at the interface of the solder bump and the UBM. This intermetallic, typically Cu.sub.6 Sn.sub.5 and or Cu.sub.3 Sn, is strong but brittle and is necessary to provide adhesion of the solder bump to the chrome-copper-gold pad metallurgy. FIG. 1 illustrates, in cross-section, a portion of a semiconductor die 10 having a solder bump 12 as formed by the process as known in the art. The solder bump 12 is deposited overlying the UBM of the bonding pad 14. The UBM is composed of a chrome layer 16, a chrome-copper layer 18, and a copper/tin intermetallic layer 20. The copper/tin intermetallic layer 20 results from the reflow process. The gold that was deposited in the chrome-copper-gold stack prior to reflow diffuses quickly through the metals during reflow so that it effectively disappears. As can be seen in FIG. 1, the solder bump is electrically connected to the underlying metal trace 22 which overlies the semiconductor substrate 24. Passivation layers 26, 28, and 30 protect the die circuitry. The UBM also seals the edges of the passivation layers.
In attaching a semiconductor die having solder bumps to a ceramic substrate or chip carrier, the bumped die is aligned to mating solder pads on the substrate. Then all the solder bumps are remelted in a second reflow process to join the die to the substrate. The reflow temperature is typically greater than 355.degree. C. Organic acid fluxes are usually dispensed around the bumps to reduce surface oxides and aid in the joining process.
If direct joining of the semiconductor die having solder bumps to copper traces on an organic PC board is desirable, lower temperature joining processes must be used to achieve the die-to-organic board attachment without damaging the PC board through exposure to excessive heat. One solution to attaching a high lead-content solder bumped semiconductor die to an organic PCB board is to selectively deposit a eutectic lead-tin solder onto specially fabricated oversized pads at the end of the traces on the board to provide large eutectic surfaces for DCA. With this option, a lower temperature can be used to join the die to the PC board because only melting and wetting of the eutectic metals on the pads on the board to the high temperature solder bumps on the die is required. The high temperature bumps do not have to melt during this process. The melted/reflowed eutectic solder wets to the solder bumps and joins them to the PC board.
Several major disadvantages are associated with the method of DCA as currently being practiced. The selective deposition of a eutectic solder pad onto the copper traces is an expensive process and one that is difficult to control due to the precision required. Complex PC boards increase the level of difficulty of this selective deposition process as well as cost. Moreover, since these eutectic solder pads are necessarily wider than the actual traces, the pitch or spacing between the traces must be increased to accommodate the pads. Since the pitch of the traces must be maintained at some minimum spacing, further reduction of die size or bump density cannot be realized which is contrary to the industry trend of miniaturization and increased board density.